Windows-only based Verilog/VHDL/SystemC/Systemverillog simulator.
Similar to Modelsim/PE, but comes with a bunch of extra design-productivity tools (block diagram editor, code2graphics converter, export-2-pdf, etc.) The core program functionality is the VHDL/Verilog-simulator -- that's what most customers use it for.
(Aldec's more-expensive simulator, Riviera, runs natively in Linux or Windows.)
The evaluation-version (7.3sp1) was released in April 2008. It is freely downloadable from Aldec's website. Just fill out the webform with a valid email-address, and Aldec will email you a working download-link.